at9933 doc.# dsfp-at9933 b061710 features ? constant current led driver ? steps input voltage up or down ? low emi ? variable frequency operation ? internal 75v linear regulator ? input and output current sensing ? input current limit ? enable & pwm dimming ? ambient temperature rating up to 125c ? meets aec-q100 requirements applications ? automotive led lighting reference documents ? aec-q 100 rev. f, 7/18/2003 ? sae j1752-3 general description the at9933 is a variable frequency pwm controller ic, designed to control an led lamp driver using a low-noise boost-buck (?uk) topology. the at9933 uses patent-pending hysteretic current-mode control to regulate both the input and the output currents. this enables superior input surge immunity without the necessity for complex loop compensation. input current control enables current limiting during startup, input under-voltage and output overload conditions. the at9933 provides a low-frequency pwm dimming input that can accept an external control signal with a duty cycle of 0 - 100% and a high dimming ratio. the at9933 based led driver is ideal for automotive led lamps. the part is rated for up to 125c ambient temperatures and is aec-q100 compliant. typical application circuit hysteretic boost-buck (?uk) led driver ic vin gate cs1 gnd vdd pwmd cs2 ref vdc l 1 l 2 c 1 q 1 d 1 r cs1 r s2 r ref2 r ref1 r s1 c 2 d 2 (optional) - vo + c 3 r cs2 d 3 r d c d at 9933 supertex inc. supertex inc. www .supertex.com
2 at9933 doc.# dsfp-at9933 b061710 ordering information device 8-lead soic 4.90x3.90mm body 1.75mm height (max) 1.27mm pitch at9933 AT9933LG-G -g indicates package is rohs compliant (green) absolute maximum ratings parameter value v in to gnd -0.5v to +75v cs1, cs2, pwmd, gate to gnd -0.3v to (v dd + 0.3v) v dd(max) 12v continuous power dissipation (t a = +25c) 8-pin soic 700mw junction temperature +150c storage temperature range -65c to +150c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifcations is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3lq&rqxudlrq ref cs2 vdd pwmd vin cs1 gnd gate 8 7 6 5 1 2 3 4 sym parameter min typ max units conditions input v indc input dc supply voltage range 1 * (2) - 75 v dc input voltage i insd shut-down mode supply current 1 - - 0.5 1.0 ma pwmd connected to gnd, v in = 12v internal regulator v dd internally regulated voltage * 7.0 7.5 9.0 v v in = 8 - 75v, i dd(ext) = 0, 500pf capacitor at gate, pwmd = gnd uvlo v dd undervoltage lockout threshold * 6.35 6.70 7.05 v v dd rising ?uvlo v dd undervoltage lockout hysteresis - - 500 - mv --- notes: 1. also limited by package power dissipation limit, whichever is lower. 2. depends on the current drawn by the part - see application section. * specifcations apply over the full operating ambient temperature range of -40oc < t a < +125oc. guaranteed by design and characterization. electrical characteristics (specifcations are at t a = 25c. v in = open, v dd = 7.5v unless otherwise noted) thermal resistance package ja 8-lead soic 128 o c/w y = last digit of year sealed ww = week sealed l = lot number = ?green? packaging yww 9933 llll product marking dg2 dg2 (top view) package may or may not include the following marks: si or supertex inc. www .supertex.com
3 at9933 doc.# dsfp-at9933 b061710 electrical characteristics (cont.)(specifcations are at t a = 25c. v in = open, v dd = 7.5v unless otherwise noted) sym description min typ max units conditions reference v ref ref pin voltage 0c < t a < +85c - 1.212 1.25 1.288 v ref bypassed with a 0.1f capacitor to gnd, i ref = 0, pwmd = 5.0v ref pin voltage -40c < t a < 125c - 1.187 1.25 1.312 v refline line regulation of reference voltage - 0 - 20 mv ref bypassed with a 0.1f capacitor to gnd, i ref = 0, v dd = 7.0 - 9.0v, pwmd = 5.0v i ref reference output current range - -0.01 - 500 a ref bypassed with a 0.1f capacitor to gnd, i ref = 0; v dd = 7.0 - 9.0v, pwmd = 5.0v v refload load regulation of reference voltage - 0 - 10 mv ref bypassed with a 0.1f capacitor to gnd, i ref = 0 - 500a, pwmd = 5.0v pwm dimming v pwmd(lo) pwmd input low voltage * - - 0.8 v v dd = 7.0 - 9.0v v pwmd(hi) pwmd input high voltage * 2.0 - - v v dd = 7.0 - 9.0v r pwmd pwmd pull-down resistance - 50 100 150 k? v pwmd = 5.0v gate i source gate short circuit current - 0.165 - - a v gate = 0v i sink gate sinking current - 0.165 - - a v gate = v dd t rise gate output rise time - - 30 50 ns c gate = 500pf t fall gate output fall time - - 30 50 ns c gate = 500pf input current sense comparator v turnon1 voltage required to turn gate on * 85 100 115 mv cs2 = 200mv; cs1 increasing; gate goes low to high v turnoff1 voltage required to turn gate off * -15 0 15 mv cs2 = 200mv; cs1 decreasing; gate goes high to low t d1,on delay to output (turn on) - - 150 250 ns cs2 = 200mv; cs1 = 50mv to +200mv step t d1,off delay to output (turn off) - - 150 250 ns cs2 = 200mv; cs1 = 50mv to -100mv step output current sense comparator v turnon2 voltage required to turn gate on * 85 100 115 mv cs1 = 200mv; cs2 increasing; gate goes low to high v turnoff2 voltage required to turn gate off * -15 0 15 mv cs1 = 200mv; cs2 decreasing; gate goes high to low t d2,on delay to output (turn on) - - 150 250 ns cs1 = 200mv; cs2 = 50mv to +200mv step t d2,off delay to output (turn off) - - 150 250 ns cs1 = 200mv; cs2 = 50mv to -100mv step notes: 1. also limited by package power dissipation limit, whichever is lower. 2. depends on the current drawn by the part - see application section. * specifcations apply over the full operating ambient temperature range of -40oc < t a < +125oc. guaranteed by design and characterization. supertex inc. www .supertex.com
4 at9933 doc.# dsfp-at9933 b061710 pin description pin number name description 1 vin this pin is the input of a 8.0 - 75v voltage regulator. 2 cs1 these pins are used to sense the input and output currents of the boost-buck converter. they are the non-inverting inputs of the internal comparators. 7 cs2 3 gnd ground return for all the internal circuitry. this pin must be electrically connected to the ground of the power train. 4 gate this pin is the output gate driver for an external n-channel power mosfet. 5 pwmd when this pin is left open or pulled to gnd, the gate driver is disabled. pulling the pin to a voltage greater than 2.0v will enable the gate drive output. 6 vdd this is a power supply pin for all internal circuits. it must be bypassed to gnd with a low esr capacitor greater than 0.1 f. 8 ref this pin provides accurate reference voltage. it must be bypassed with a 0.01 - 0.1 f capacitor to gnd. block diagram regulator 7.5v vin cs1 cs2 pwmd gate vdd ref gnd 1.25v at9933 input comparator output comparator 0mv 100mv supertex inc. www .supertex.com
5 at9933 doc.# dsfp-at9933 b061710 power topology the at9933 is optimized to drive a continuous conduction mode (ccm) boost-buck dc/dc converter topology com - monly referred to as ?uk converter (see circuit diagram on page 1). this power converter topology offers numerous advantages useful for driving high-brightness light emitting diodes (hb led). these advantages include step-up or step-down voltage conversion ratio and low input and output current ripple. the output load is decoupled from the input voltage with a capacitor making the driver inherently failure- safe for the output load. the at9933 offers a simple and effective control technique for use with a boost-buck led driver. it uses two hysteretic mode controllers C one for the input and one for the output. the outputs of these two hysteretic comparators are and - ed and used to drive the external fet. this control scheme gives accurate current control and constant output current in the presence of input voltage transients without the need for complicated loop design. input voltage regulator the at9933 can be powered directly from its vin pin that takes a voltage up to 75v. when a voltage is applied at the vin pin, the at9933 seeks to regulate a constant 7.5v (typ) at the vdd pin. the regulator also has a built in under-volt - age lockout which shuts off the ic if the voltage at the vdd pin falls below the uvlo threshold. the vdd pin must be bypassed by a low esr capacitor (0.1f) to provide a low impedance path for the high fre - quency current of the output gate driver. the input current drawn from the v in pin is a sum of the 1ma current drawn by the internal circuit and the current drawn by the gate driver (which in turn depends on the switching frequency and the gate charge of the external fet). i in = 1.0ma + q g ?f s (1) in the above equation, f s is the switching frequency and q g is the gate charge of the external fet (which can be ob - tained from the datasheet of the fet). minimum input voltage at vin pin the minimum input voltage at which the converter will start and stop depends on the minimum voltage drop required for the linear regulator. the internal linear regulator will regulate the voltage at the vdd pin when v in is between 8.0 and 75v. however, when v in is less than 8.0v, the converter will still function as long as v dd is greater than the under voltage lockout. thus, under certain conditions, the converter will be able to start at v in voltages of less than 8.0v. the start/stop voltages at the vin pin can be determined using the maxi - mum voltage drop across the linear regulator as a function of the current drawn. this data is shown in fig. 1 for ambient temperatures of 25oc and 125oc. assume an ambient temperature of 125c. assuming the ic is driving a 15nc gate charge fet at 300khz, the total input current is estimated to be 5.5ma (using eqn. 1). at this input current, the maximum voltage drop from fig. 1 can be ap- proximately estimated to be v drop = 2.7v. however, before the ic starts switching the current drawn will be 1.0ma. at this current level, the voltage drop is approximately v drop1 = 0.5v. thus, the start/stop v in voltages can be computed to be: v in-start = uvlo max + v drop1 = 6.95v + 0.5v = 7.45v v in-stop = uvlo max - uvlo + v drop = 6.95 - 0.5v + 2.7v = 9.15v note that in this case, since the gate drive draws too much current, v in-start is less than v in-stop . in such cases, the con - trol ic will oscillate between on and off if the input voltage is between the start and stop voltages. in these circumstances, it is recommended that the input voltage be kept higher than v in-stop (in this case the ic will operate normally if the input voltage is kept higher than 9.2v). in case of input transients that reduce the input voltage be - low 8.0v (like cold crank condition in an automotive system), the vin pin of the at9933 can be connected to the drain of the mosfet through a switching diode with a small (1.0nf) capacitor between vin and gnd (as long as the drain volt - age does not exceed 75v). since the drain of the fet is at a voltage equal to the sum of the input and output voltages, the ic will still be operational when the input goes below 8v. in these cases, a larger capacitor is needed to the vdd pin to supply power to the ic when the mosfet is on. functional description voltage drop vs. i in 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 4 5 6 7 i in (m a) voltage drop (v ) fig. 1. maximum vo ltage drop vs. input curren t 125 o c 25 o c supertex inc. www .supertex.com
6 at9933 doc.# dsfp-at9933 b061710 in this case v dd uvlo cannot be relied upon to turn off the ic at low input voltages when input current levels can get too large. the input current limit must then be designed to limit the input current to safe levels during input undervoltage conditions. reference an internally trimmed voltage reference of 1.25v is provided at the ref pin. the reference can supply a maximum output current of 500a to drive external resistor dividers. this reference can be used to set the current thresholds of the two comparators as shown in the typical application cir - cuit. current comparators the at9933 features two identical comparators with a built- in 100mv hysteresis. when the gate is low, the inverting terminal is connected to 100mv and when the gate is high, it is connected to gnd. one comparator is used for the input current control and the other for the output current control. the input side hysteretic controller is in operation during start-up, overload and input undervoltage conditions. this ensures that the input current never exceeds the designed value. during normal operation, the input current will be less than the programmed current and hence, the output of the input side comparator will be high. the output of the and gate will then be dictated by the output current controller. the output side hysteretic comparator will be in operation during the steady state operation of the circuit. this com - parator turns the mosfet on and off based on the led current. pwm dimming pwm dimming can be achieved by applying a ttl-compat - ible square wave signal at the pwm pin. when the pwmd pin is pulled high, the gate driver is enabled and the circuit operates normally. when the pwmd pin is left open or con - nected to gnd, the gate driver is disabled and the external mosfet turns off. the ic is designed so that the signal at the pwmd pin inhibits the driver only and the ic need not go through the entire start-up cycle each time ensuring a quick response time for the output current. the recommended pwm dimming frequency range is from 100hz to a few kilo hertz. the fying capacitor in the ?uk converter (c1) is initially charged to the input voltage vdc (through diodes d 1 and d 2 ). when the circuit is turned on and reaches steady state, the voltage across c 1 will be vdc+vo. in the absence of diode d 2 , when the circuit is turned off, capacitor c 1 will discharge through the leds and the input voltage source vdc. thus, during pwm dimming, if capacitor c 1 has to be charged and discharged each cycle, the transient response of the circuit will be limited. by adding diode d 2 , the voltage across capac- itor c 1 is held at vdc+vo even when the circuit is turned off enabling the circuit to return quickly to its steady state (and bypassing the start-up stage) upon being enabled. application information over-voltage protection over-voltage protection can be added by splitting the output side resistor r s2 into two components and adding a zener diode d 3 (see the design example circuit on the following page). when there is an open led condition, the diode d 3 will clamp the output voltage and the zener diode current will be regulated by the sum of r s2a and r cs2 . damping circuit the ?uk converter is inherently unstable when the output current is being controlled. an uncontrolled input current will lead to an un-damped oscillation between l 1 and c 1 causing excessively high voltages across c 1 . to prevent these oscil - lations, a damping circuit consisting of r d and c d is applied across the capacitor c 1 . this damping circuit will stabilize the circuit and help in the proper operation of the at9933 based ?uk converter. design and operation of the boost-buck converter for details on the design for a boost-buck converter using the at9933 and the calculation of the damping components, please refer to application note an-h51 and an-h58. supertex inc. www .supertex.com
7 at9933 doc.# dsfp-at9933 b061710 design example the choice of the resistor dividers to set the input and output current levels is illustrated by means of the design example given below. the parameters of the power circuit are: v in min = 9.01v v in max = 16v v o = 28v i o = 0.35a f s min = 300khz using these parameters, the values of the power stage in - ductors and capacitor can be computed as (see application note an-h51 for details): l1 = 82h l2 = 150h c1 = 0.22f the input and output currents for this design are: i in max = 1.6a i in = 0.21a i o = 350ma i o = 87.5ma current limits the current sense resistor ( r cs2 ), combined with the other resistors (r s2 & r ref2 ), determines the output current limits. the current sense resistor ( r cs1 ), combined with the other resistors (r s1 & r ref1 ), determines the input current limits. the resistors can be chosen using the following equations: i x r cs = 1.2v x (r s / r ref ) - 0.05v (2) i x r cs = 0.1v x (r s / r ref ) + 0.1v (3) where i is the current (either i o or i in ) and i is the peak-to- peak ripple in the current (either i o or i in ). for the input side, the current level used in the equations should be larger than the maximum input current so that it does not interfere with the normal operation of the circuit. the peak input current can be computed as: i in,pk = i in,max + (i in / 2) = 1.706a (4) design example circuit vin gate cs1 gnd vdd pwmd cs2 ref vdc l 1 l 2 c 1 q 1 d1 r cs1 r s2a r ref2 r ref1 r s1 c 2 d 2 (optional) - vo + c 3 r cs2 c o r d c d at 9933 r s2b d 3 supertex inc. www .supertex.com
8 at9933 doc.# dsfp-at9933 b061710 assuming a 30% peak-to-peak ripple when the converter is in input current limit mode, the minimum value of the input current will be: i lim,min = 0.85 ? i in,lim (5) setting i lim,min = 1.05 ? i in,pk (6) the current level to limit the converter can then be com - puted. i in,lim = (1.05 / 0.85) x i in,pk = 2.1a (7) using i o = 350ma and i o = 87.5ma in (1) and (2), r cs2 = 1.78 r s2 / r ref2 = 0.5625 before the design of the output side is complete, over voltage protection has to be included in the design. for this applica - tion, choose a 33v zener diode. this is the voltage at which the output will clamp in case of an open led condition. for a 350mw diode, the maximum current rating at 33v works out to about 10ma. using a 2.5ma current level during open led conditions, and assuming the same r s2 /r ref2 ratio, r cs2 + r s2a = 120 (8) choose the following values for the resistors: r cs2 = 1.65, 1/4w, 1% r ref2 = 10k, 1/8w, 1% r s2a = 100, 1/8w, 1% r s2b = 5.23k, 1/8w, 1% the current sense resistor needs to be at least a 1/4w, 1% resistor. similarly, using i in = 2.1a and i in = 0.3xi in = 0.63 in (1) and (2): r s1 / r ref1 = 0.442 r cs1 = 0.228 p rcs1 = i 2 in,lim ? r cs1 = 1w choose the following values for the resistors: r cs1 = parallel combination of three 0.68, 1/2w, 5% resistors r ref1 = 10k, 1/8w, 1% r s1 = 4.42k, 1/8w, 1% supertex inc. www .supertex.com
9 at9933 (the package drawing(s) in this data sheet may not refect the most current specifcations. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-at9933 b061710 8-lead soic (narrow body) package outline (lg) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch 1 8 seating plane gauge plane l l1 l2 e e1 d e b a a2 a1 seating plane a a t op vi ew side v iew vi ew b v iew b 1 note 1 (index area d/2 x e1/2) vi ew a-a h h note 1 symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension pp min 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 4.90 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation aa, issue e, sept. 2005. * this dimension is not specifed in the jedec drawing. drawings are not to scale. supertex doc. #: dspd-8solgtg, version i041309. note: 1. this chamfer feature is optional. a pin 1 identifer must be located in the index area indicated. the pin 1 identifer can be: a molded mark/identifer; an embedded metal marker; or a printed indicator. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry an d specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. (website: http//www. supertex.com) ?2012 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com
|
